This invention relates generally to computer memory, and more specifically, to writing to memory using shared address buses.
Limited lifetime computer storage devices include, but are not limited to, flash memory (e.g., not-and or “NAND” flash memory, and not-or or “NOR” flash memory) and phase change memory (PCM). Limited lifetime memory technologies may benefit from iterative write techniques (commonly referred to as “write-and-verify”) that are comprised of a sequence of write and read operations. Iterative write techniques may allow a controller for the memory to store a desired value with an increased accuracy, since the read operations offer a feedback mechanism that can be used to reduce errors in the writing process. Such increased accuracy is particularly relevant when the storage of more than one bit per cell is desired. A drawback of write-and-verify techniques is that the iterative process consumes additional resources in the memory. For example, the write bandwidth gets reduced in a manner proportional to the number of attempts it takes to store a value in the memory.